Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit. Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask).
As noted, microlithography is a central step in the manufacturing of semiconductor integrated circuits, where patterns formed on semiconductor wafer substrates define the functional elements of semiconductor devices, such as microprocessors, memory chips etc. Similar lithographic techniques are also used in the formation of flat panel displays, micro-electro mechanical systems (MEMS) and other devices.
As semiconductor manufacturing processes continue to advance, the dimensions of circuit elements have continually been reduced while the amount of functional elements, such as transistors, per device has been steadily increasing over decades, following a trend commonly referred to as ‘Moore's law’. At the current state of technology, critical layers of leading-edge devices are manufactured using optical lithographic projection systems known as scanners that project a mask image onto a substrate using illumination from a deep-ultraviolet laser light source, creating individual circuit features having dimensions well below 100 nm, i.e. less than half the wavelength of the projection light.
This process, in which features with dimensions smaller than the classical resolution limit of an optical projection system are printed, is commonly known as low-k1 lithography, according to the resolution formula CD=k1×λ/NA, where λ is the wavelength of radiation employed (currently in most cases 248 nm or 193 nm), NA is the numerical aperture of the projection optics, CD is the ‘critical dimension’—generally the smallest feature size printed—and k1 is an empirical resolution factor. In general, the smaller k1, the more difficult it becomes to reproduce a pattern on the wafer that resembles the shape and dimensions planned by a circuit designer in order to achieve particular electrical functionality and performance. To overcome these difficulties, sophisticated fine-tuning steps are applied to the projection system as well as to the mask design. These include, for example, but not limited to, optimization of NA and optical coherence settings, customized illumination schemes, use of phase shifting masks, optical proximity correction in the mask layout, or other methods generally defined as ‘resolution enhancement techniques’ (RET).
As one important example, optical proximity correction (OPC, sometimes also referred to as ‘optical and process correction’) addresses the fact that the final size and placement of a printed feature on the wafer will not simply be a function of the size and placement of the corresponding feature on the mask. It is noted that the terms ‘mask’ and ‘reticle’ are utilized interchangeably herein. For the small feature sizes and high feature densities present on typical circuit designs, the position of a particular edge of a given feature will be influenced to a certain extent by the presence or absence of other adjacent features. These proximity effects arise from minute amounts of light coupled from one feature to another. Similarly, proximity effects may arise from diffusion and other chemical effects during post-exposure bake (PEB), resist development, and etching that generally follow lithographic exposure.
In order to ensure that the features are generated on a semiconductor substrate in accordance with the requirements of the given target circuit design, proximity effects need to be predicted utilizing sophisticated numerical models, and corrections or pre-distortions need to be applied to the design of the mask before successful manufacturing of high-end devices becomes possible. The article “Full-Chip Lithography Simulation and Design Analysis—How OPC Is Changing IC Design”, C. Spence, Proc. SPIE, Vol. 5751, pp 1-14 (2005) provides an overview of current ‘model-based’ optical proximity correction processes. In a typical high-end design almost every feature edge requires some modification in order to achieve printed patterns that come sufficiently close to the target design. These modifications may include shifting or biasing of edge positions or line widths as well as application of ‘assist’ features that are not intended to print themselves, but will affect the properties of an associated primary feature.
The application of model-based OPC to a target design requires good process models and considerable computational resources, given the many millions of features typically present in a chip design. However, applying OPC is generally not an ‘exact science’, but an empirical, iterative process that does not always resolve all possible weaknesses on a layout. Therefore, post-OPC designs, i.e. mask layouts after application of all pattern modifications by OPC and any other RET's, need to be verified by design inspection, i.e. intensive full-chip simulation using calibrated numerical process models, in order to minimize the possibility of design flaws being built into the manufacturing of a mask set. This is driven by the enormous cost of making high-end mask sets, which run in the multi-million dollar range, as well as by the impact on turn-around time by reworking or repairing actual masks once they have been manufactured.
Both OPC and full-chip RET verification may be based on numerical modeling systems and methods as described, for example in, U.S. Pat. No. 7,003,758 and an article titled “Optimized Hardware and Software For Fast, Full Chip Simulation”, by Y. Cao et al., Proc. SPIE, Vol. 5754, 405 (2005).
While full-chip numerical simulation of the lithographic patterning process has been demonstrated at a single process condition, typically best focus and best exposure dose or best ‘nominal’ condition, it is well known that manufacturability of a design requires sufficient tolerance of pattern fidelity against small variations in process conditions that are unavoidable during actual manufacturing. This tolerance is commonly expressed as a process window, defined as the width and height (or ‘latitude’) in exposure-defocus space over which CD or edge placement variations are within a predefined margin (i.e., error tolerance), for example ±10% of the nominal line width. In practice, the actual margin requirement may differ for different feature types, depending on their function and criticality. Furthermore, the process window concept can be extended to other basis parameters in addition to or besides exposure dose and defocus.
Manufacturability of a given design generally depends on the common process window of all features in a single layer. While state-of-the-art OPC application and design inspection methods are capable of optimizing and verifying a design at nominal conditions, it has been recently observed that process-window aware OPC models will be required in order to ensure manufacturability at future process nodes due to ever-decreasing tolerances and CD requirements.
Currently, in order to map out the process window of a given design with sufficient accuracy and coverage, simulations at N parameter settings (e.g., defocus and exposure dose) are required, where N can be on the order of a dozen or more. Consequently, an N-fold multiplication of computation time is necessary if these repeated simulations at various settings are directly incorporated into the framework of an OPC application and verification flow, which typically will involve a number of iterations of full-chip lithography simulations. However, such an increase in the computational time is prohibitive when attempting to validate and/or design a given target circuit.
As such, there is a need for simulation methods and systems which account for variations in the process-window that can be used for OPC and RET verification, and that are more computationally efficient than such a ‘brute-force’ approach of repeated simulation at various conditions as is currently performed by known prior art systems.
PCT Patent App. No. US2009/049792 describes an efficient methodology for dense process window simulation and addresses the need for process-window aware RET verification. What remains desirable is to obtain a methodology for OPC based on the efficient dense process window simulation to maximize the process window for full chip design.